STM32W108HB datasheet(222/278 Pages) STMICROELECTRONICS

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Analog-to-digital converter

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Table 39 shows the typical configurations of ADC inputs.

ADC0

VREF/2

Single-ended

ADC1

VREF/2

Single-ended

ADC2

VREF/2

Single-ended

ADC3

VREF/2

Single-ended

ADC4

VREF/2

Single-ended

ADC5

VREF/2

Single-ended

ADC1

ADC0

Differential(1)

ADC3

ADC2

Differential(1)

ADC5

ADC4

Differential(1)

GND

VREF/2

Calibration

VREF

VREF/2

Calibration

VDD_PADSA/2

VREF/2

Calibration

Input range

ADC inputs can be routed through input buffers to expand the input voltage range. The input

buffers have a fixed 0.25 gain and the converted data is scaled by that factor.

With the input buffers disabled the single-ended input range is 0 to VREF and the differential

input range is -VREF to +VREF. With the input buffers enabled the single-ended range is 0

to VDD_PADS and the differential range is -VDD_PADS to +VDD_PADS.

The input buffers are enabled for the ADC P and N inputs by setting the HVSELP and

HVSELN bits respectively, in the ADC_CR register. The ADC accuracy is reduced when the

input buffer is selected.

Sample time

ADC sample time is programmed by selecting the sampling clock and the clocks per

sample.

●

The sampling clock may be either 1 MHz or 6 MHz. If the CLK bit in the ADC_CR

MHz sample clock offers faster conversion times but the ADC resolution is lower than

that achieved with the 1 MHz clock.

●

The number of clocks per sample is determined by the SMP[2:0] bits in the ADC_CR

Longer sample times produce more significant bits. Regardless of the sample time,

converted samples are always 16-bits in size with the significant bits left-aligned within

the value.

Table 39.

Typical ADC input configurations

ADC P input

ADC N input

CHSELP[3:0]

CHSELN[3:0]

Purpose

The differential is only in LV mode.

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