STM32W108HB datasheet(226/278 Pages) STMICROELECTRONICS

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Analog-to-digital converter

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

226/278

Doc ID 16252 Rev 14

11.2

Interrupts

Four kinds of ADC events can generate an ADC interrupt, and each has a bit flag in the

ADC_ISR register to identify the reason(s) for the interrupt:

●

DMAOVF – an ADC conversion result was ready but the DMA was disabled (DMA

buffer overflow).

●

SAT – the gain correction multiplication exceeded the limits for a signed 16-bit number

(gain saturation).

●

DMABF – the DMA wrote to the last location in the buffer (DMA buffer full).

●

DMABHF – the DMA wrote to the last location of the first half of the DMA buffer (DMA

buffer half full).

Bits in ADC_ISR may be cleared by writing a 1 to their position.

The ADC_IER register controls whether or not ADC_ISR bits actually request the ARM®

Cortex-M3 ADC interrupt; only the events whose bits are 1 in ADC_IER can do so.

For non-interrupt (polled) ADC operation set ADC_IER to zero, and read the bit flags in

ADC_ISR to determine the ADC status.

Note:

When making changes to the ADC configuration it is best to disable the DMA beforehand. If

this isn’t done it can be difficult to determine at which point the sample data in the DMA

buffer switch from the old configuration to the new configuration. However, since the ADC

will be left running, if it completes a conversion after the DMA is disabled, the DMAOVF flag

will be set. To prevent these unwanted DMA buffer overflow indications, clear the DMAOVF

flag immediately after enabling the DMA, preferably with interrupts off. Disabling the ADC in

addition to the DMA is often undesirable because of the additional analog startup time when

it is re-enabled.

STM32W108HB Datasheet(PDF) 226 Page - STMicroelectronics