HC08KL8GRSSLASHD datasheet(64/256 Pages) NXP

64 / 256 page

Central Processor Unit (CPU)

General Release Specification

MC68HC08KL8 — Rev. 2.0

Central Processor Unit (CPU)

NOTE:

To maintain M6805 Family compatibility, the upper byte of the index

modifies H, then the user must stack and unstack H using the PSHH and

PULH instructions.

After the I bit is cleared, the highest-priority interrupt request is

serviced first.

A return-from-interrupt (RTI) instruction pulls the CPU registers from

the stack and restores the interrupt mask from the stack. After any

reset, the interrupt mask is set and can only be cleared by the clear

interrupt (CLI) mask software instruction.

N — Negative flag

The CPU sets the negative flag when an arithmetic operation, logic

operation, or data manipulation produces a negative result, setting

bit 7 of the result.

1 = Negative result

0 = Non-negative result

Z — Zero flag

The CPU sets the zero flag when an arithmetic operation, logic

operation, or data manipulation produces a result of $00.

1 = Zero result

0 = Non-zero result

C — Carry/Borrow Flag

The CPU sets the carry/borrow flag when an addition operation

produces a carry out of bit 7 of the accumulator or when a subtraction

operation requires a borrow. Some instructions — such as bit test and

branch, shift, and rotate — also clear or set the carry/borrow flag.

1 = Carry out of bit 7

0 = No carry out of bit 7

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC08KL8GRS/D Datasheet(PDF) 64 Page - NXP Semiconductors