HC08KL8GRSSLASHD datasheet(96/256 Pages) NXP

96 / 256 page

System Integration Module (SIM)

General Release Specification

MC68HC08KL8 — Rev. 2.0

System Integration Module (SIM)

8.7 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low-power

mode for standby situations. The SIM holds the CPU in a non-clocked

state. The operation of each of these modes is described here. Both

STOP and WAIT clear the interrupt mask (I) in the condition code

8.7.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks

continue to run. Figure 8-14 shows the timing for wait mode entry.

A module that is active during wait mode can wake up the CPU with an

interrupt if the interrupt is enabled. Stacking for the interrupt begins one

cycle after the WAIT instruction during which the interrupt occurred. In

wait mode, the CPU clocks are inactive. Refer to the wait mode

subsection of each module to see if the module is active or inactive in

wait mode. Some modules can be programmed to be active in wait

mode.

Wait mode can also be exited by a reset or break. A break interrupt

during wait mode sets the SIM break stop/wait bit, SBSW, in the break

status register (BSR). If the COP disable bit, COPD, in the mask option

is enabled and remains active in wait mode.

Figure 8-14. Wait Mode Entry Timing

WAIT ADDR + 1

SAME

IAB

IDB

PREVIOUS DATA

NEXT OPCODE

SAME

WAIT ADDR

SAME

R/W

NOTE: Previous data can be operand data or the WAIT opcode, depending on the

last instruction.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC08KL8GRS/D Datasheet(PDF) 96 Page - NXP Semiconductors