AT25QL641 datasheet(79/80 Pages) RENESAS

79 / 80 page

DS-AT25QL641-130 Rev. G

Page 79

Sep 14, 2022

AT25QL641 Datasheet

12.1 Errata:

1. If Status Register-2 CMP bit is 0, and Status Register-1 bits {SEC,TB,BP2,BP1,BP} are {1,0,0,0,1}, address

7FF000h-7FFFFFh is protected from any Program or Erase commands. However, this setting does not protect

the rest of Sector 127 or the rest of Block 255 from 64-kbit or 32-kbit Block Erase commands. If a 64-kbit Block

Erase Command is issued to Sector 127, address 7F0000h-7FEFFFh is be erased. If a 32-kbit Block Erase

Command is issued to Block 255, address 7F8000h-7FEFFFh is be erased.

Workaround: If this protection bit combination is used and the behavior described in Note 3 is required, avoid

using 64-kbit or 32-kbit Block Erase commands for this specific memory region.

2. If Status Register-2 CMP bit is 1, and Status Register-1 bits {SEC,TB,BP2,BP1,BP} are {1,1,0,0,1}, address

001000h-7FFFFFh is protected from any Program or Erase commands. However, this setting does not protect

the rest of Sector 0 or the rest of Block 0 from 64-kbit or 32-kbit Block Erase commands. If a 64-kbit Block Erase

Command is issued to Sector 0, address 000000h-000FFFh is be erased. If a 32-kbit Block Erase Command is

issued to Block 0, address 000000h-000FFFh is be erased.

Workaround: If this protection bit combination is used and the behavior described in Note 3 is required, avoid

using 64-kbit or 32-kbit Block Erase commands for this specific memory region.

AT25QL641 Datasheet(PDF) 79 Page - Renesas Technology Corp