M95P16-EXCSSLASHEF datasheet(9/63 Pages) STMICROELECTRONICS

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Signal description

During device operation, VCC must be held stable and within the specified valid range VCC(min) to VCC(max).

All the input and output signals, described in the following sections, must be held high or low (according to VIH,

VOH, VIL, VOL voltages specified in Table 25. DC characteristics - Other parameters).

3.1

Serial data output (Q-DQ1)

This output is a push-pull buffer. The signal is used to transfer data out of the device, serially. Data are shifted out

on the falling edge of Serial clock (C).

With the Dual output and Quad output read commands, this pin remains an output pin (DQ1) in conjunction with

other pins, to allow four bits of data on DQ0-3 to be clocked out on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the Data output Q (DQ1) pin is referenced to as MISO,

unless specifically addressing the Dual output and Quad output modes (in this case it is referenced as DQ1).

The serial output pin is in high-Z whenever the device is deselected (S is deasserted).

3.2

Serial data input (D-DQ0)

This is a CMOS input/output with no internal pull-up/down. The signal is used to transfer data into the device,

serially. It receives instructions, addresses and the data to be written. Values are latched on the rising edge of

Serial clock (C).

With the Dual-output and Quad-output read commands, this pin becomes a push/pull output buffer (DQ0), in

conjunction with other pins, to allow four bits of data on DQ0-3 to be clocked out on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the Data input D (DQ0) pin is referenced as MOSI.

The D pin is in a high-impedance state whenever the device is deselected (S is deasserted).

3.3

Serial clock (C)

This is a CMOS input with no internal pull up/down. This signal synchronizes the timing of the serial interface. The

instructions, the addresses, or the data present on the serial data input (D) are latched on the rising edge of the

serial clock (C), while the output data on the DQn pins is changed after the falling edge of the serial clock (C).

3.4

Chip select (S)

This is a CMOS input with no internal pull up/down. When this signal is high, the device is deselected and

Serial data outputs (DQ0-3) are in high impedance. The device is in Standby power mode (not Deep power-down

mode), unless an internal Write cycle is in progress.

Driving Chip select (S) low selects the device, putting it in Active power mode.

After power-up, a falling edge on Chip select (S) is required prior to the start of any instruction. A low to high

transition is required to end an operation.

An external pull-up on S is required so that, at power-up, voltage on S follows the power supply voltage on VCC.

3.5

Hold (HOLD-DQ3)

This pin is a CMOS input with no internal pull-up/down, and a push-pull output buffer. This signal is used to pause

all serial communications with the device, without deselecting it.

During the Hold condition, the Serial data output (Q) is high-Z, while the Serial data input (D) and Serial clock (C)

are Don’t care.

To start the Hold condition, the device must be selected by driving Chip select (S) low.

When the device is selected with HOLD low and C high, it switches into the Hold condition when C transits low.

The HOLD pin supports dual and quad output reads (see Section 4.3 and Section 4.4).

With the fast read quad output command, the HOLD function is no longer available after the last bit of the third

address bytes of the command, and the HOLD pin becomes an output pin (DQ3). In conjunction with other pins,

this allows four-bit data to be clocked into DQ3 on every falling edge of SCK.

For consistency with the SPI nomenclature, this pin is referred to as the HOLD pin, unless specifically addressing

the Quad output mode, in which case it is referred to as DQ3.

M95P16-I M95P16-E

Signal description

DS13710 - Rev 1

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