M95P16-EXCSSLASHEF datasheet(20/63 Pages) STMICROELECTRONICS

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Table 10. Volatile register format

x(1)

BUFEN

BUFLD

1. x: Don't care bit.

Buffer loading activation (BUFEN) bit

This Buffer mode is activated by setting the volatile configuration bit (BUFEN) to 1 with a WREN + WRVR

instruction.

When this bit is set to 1, it allows Page program instruction decoding and buffering while a previous Program

instruction is executing. When this bit is at 0, a Page program instruction is not decoded while the program is

being executed. At power-up, or after Software reset instruction, this flag is cleared to 0.

Buffer loading status (BUFLD) bit

When this bit is at 0, the buffer is free and accepts the loading of a new Page program instruction. When this bit is

at 1, the buffer is full and a Page program instruction is discarded and lost.

This bit:

•

is set to 1 at power up

•

switches to 0 when BUFEN is set to 1

•

is automatically set to 1 when BUFEN is 0

5.4

SFDP register format

The device features a 512-byte serial flash discoverable parameter (SFDP) register that contains information

about device configuration, available instructions, and other features, in a standard set of internal parameter

tables.

These parameter tables can be interrogated by host-system software, enabling the adjustments needed to

accommodate divergent features from multiple vendors.

The Read SFDP register instruction is compatible with the SFDP standard and with the JEDEC standard

JESD216.

M95P16-I M95P16-E

SFDP register format

DS13710 - Rev 1

page 20/63

M95P16-EXCS/EF Datasheet(PDF) 20 Page - STMicroelectronics