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M95P16-EXCS/EF Datasheet(PDF) 24 Page - STMicroelectronics

Part # M95P16-EXCS/EF
Description  Ultra low power 16 Mbit serial SPI page EEPROM with dual and quad outputs
PDF  63 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95P16-EXCS/EF Datasheet(HTML) 24 Page - STMicroelectronics

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6.5
Clear Safety register (50h)
The Clear Safety register (CLRSF) instruction resets all the bits of the Safety register.
This instruction is entered (without address) by driving S low, shifting the instruction code 50h into the Data input
(D) pin on the rising edge of C. The instruction is completed by driving S high.
As soon as S goes high, the device resets immediately all volatile bits of the Safety register.
The S pin must be driven high after the eighth bit has been latched. If this is not done the instruction is not
executed.
Figure 11. Clear Safety register
CLRSF instruction
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
High impedance
C
D
Q
S
MS54397V1
6.6
Read Volatile register (85h)
The Read Volatile register (RDVR) instruction is used to read the 8-bit Volatile register.
The instruction is entered by driving S low and shifting the instruction code 35h into the D pin on the rising edge
of C. The volatile register bits are then shifted out (MSB first) on the Q pin, on the falling edge of C. The Volatile
register can be read continuously, as shown in Figure 12. Read Volatile register. The instruction is completed by
driving S high.
The Read Volatile register instruction can be used at any time, even while a Program, Erase or Write Status
register cycle is in progress.
Refer to Status, Configurable, Safety, Volatile and SFDP registers for the register description.
Figure 12. Read Volatile register
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
High impedance
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
C
D
S
Q
RDVR instruction
Volatile byte
Volatile byte
MS55403V1
M95P16-I M95P16-E
Clear Safety register (50h)
DS13710 - Rev 1
page 24/63



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