M95P16-EXCSSLASHEF datasheet(16/63 Pages) STMICROELECTRONICS

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4.12.2

Hardware data protection

Hardware data protection is implemented using the write protect signal applied on the W pin. This freezes the

non-volatile bits of the Status register in a read-only mode. In this mode, the block protection bits (BPn), the

top/bottom bit (TB), and the Status register write disable bit (SRWD) are protected (for further details, refer to

Section 5.1 Status register).

Table 5. Protection modes

SRWD

bit

Mode

Write protection of the Status register

Memory content(1)

Protected area

Unprotected area

Software

protected

(SPM)

•

Status register can be written (if the

WREN instruction has set the WEL bit).

•

BP2, BP1, BP0 and TB bits can be

changed

Write- protected

Ready to accept

Write instructions

Hardware

protected

(HPM)

•

Status register is hardware write-

protected.

•

BP2, BP1, BP0 and TB bits cannot be

changed.

1. As defined by the values in the block protection (BP2, BP1, BP0) and TB bits of the Status register.

4.13

Polling during a Program, Write or Erase cycle

A reduction in the time taken to complete the following commands is possible by not waiting for the worst-case

delay (tPW, tWSCR, tPP, tSE, tBE, or tCE) to elapse (see Table 26. Programming times):

•

Write

•

Write Status register

•

Program

•

Erase (Page, Sector, Block and Chip erase)

The write in progress (WIP) bit in the Status register is provided so that the application program can monitor

whether the Write, Program or Erase cycle is complete (refer to Section 5.1 Status register).

M95P16-I M95P16-E

Polling during a Program, Write or Erase cycle

DS13710 - Rev 1

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