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DSP56600FM/AD Datasheet(PDF) 21 Page - NXP Semiconductors

Part # DSP56600FM/AD
Description  INTEGRATED CELLULAR BASEBAND PROCESSOR
PDF  76 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

DSP56600FM/AD Datasheet(HTML) 21 Page - NXP Semiconductors

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DSP56652
DSP56652 Signal Description
Preliminary
MOTOROLA
DSP56652 Technical Data Sheet
1-15
Data Bus
Bus Control
Table 1-8
Data Bus Signals
Signal
Names
Signal
Type
State
during
Reset
Signal Description
D0ÐD15
Input/
Output
Input
Data bus
ÑThese signals provide the bidirectional data bus for
external memory accesses. D0ÐD15 are held in the previous logic
state when there is no external bus activity and during hardware
reset. This is done with weak ÒkeepersÓ inside the I/O buffers.
Table 1-9
Bus Control Signals
Signal
Name
Signal
Type
State
during
Reset
Signal Description
R/W
Output
Driven
high
Read/writeÑ
This signal indicates the bus access type. A high signal
indicates a bus read. A low signal indicates a write to the bus. When
accessing memory it can also be used as write enable (WE) signal. When
accessing a peripheral chip, the signal acts as a read/write.
EB0
Output
Driven
high
Enable byte 0
ÑWhen driven low, this signal indicates access to data
byte 0 (D8ÐD15) during a read or write cycle. This pin may also act as a
write byte enable, if so programmed. This output is used when accessing
16-bit wide SRAM.
EB1
Output
Driven
high
Enable byte 1
ÑWhen driven low, this signal indicates access to data
byte 1 (D0ÐD7) during a read or write cycle. This pin may also act as a
write byte enable, if so programmed. This output is used when accessing
16-bit wide SRAM.
OE
Output
Driven
high
Bus selectÑ
When driven low, this signal indicates that the current bus
access is a read cycle and enables slave devices to drive the data bus with
a read.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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