 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DSP56600FM/AD Datasheet(PDF) 57 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
DSP56600FM/AD Datasheet(HTML) 57 Page - NXP Semiconductors |
|
|
57 / 76 page  DSP56652 Audio Serial Codec and Baseband Serial Codec Timing Preliminary MOTOROLA DSP56652 Technical Data Sheet 2-15 445 Flags input hold time after RXC falling edge Ñ Ñ 7.3 0.0 Ñ Ñ x ck i ck s ns ns 446 TXC rising edge to FST out (bl) high Ñ Ñ Ñ Ñ 35.4 18.3 x ck i ck ns ns 447 TXC rising edge to FST out (bl) low Ñ Ñ Ñ Ñ 37.8 20.7 x ck i ck ns ns 448 TXC rising edge to FST out (wr) high2 ÑÑ Ñ Ñ 37.8 20.7 x ck i ck ns ns 449 TXC rising edge to FST out (wr) low2 ÑÑ Ñ Ñ 40.3 23.2 x ck i ck ns ns 450 TXC rising edge to FST out (wl) high Ñ Ñ Ñ Ñ 36.6 19.5 x ck i ck ns ns 451 TXC rising edge to FST out (wl) low Ñ Ñ Ñ Ñ 37.8 20.7 x ck i ck ns ns 452 TXC rising edge to data out enable from high impedance ÑÑ Ñ Ñ 37.8 20.7 x ck i ck ns ns 454 TXC rising edge to data out valid Ñ 35 + 0.5 ´ TDC Ñ Ñ 43.5 25.6 x ck i ck ns ns 455 TXC rising edge to data out high impedance3 ÑÑ Ñ Ñ 37.8 19.5 x ck i ck ns ns 457 FST input (bl, wr) setup time before TXC falling edge2 Ñ Ñ 2.0 21.0 Ñ Ñ x ck i ck ns ns 458 FST input (wl) to data out enable from high impedance3 Ñ Ñ Ñ 32.9 ns 460 FST input (wl) setup time before TXC falling edge Ñ Ñ 2.0 21.0 Ñ Ñ x ck i ck ns ns 461 FST input hold time after TXC falling edge Ñ Ñ 4.0 0.0 Ñ Ñ x ck i ck ns ns 462 Flag output valid after TXC rising edge Ñ Ñ Ñ Ñ 39.0 22.0 x ck i ck ns ns Note: 1. For internal clock, external clock cycle is defined by ICYC and BBP/SAP control register. 2. Word relative frame sync signal wave form, relates to clock, as the bit length frame sync signal wave form, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 3. Periodically sampled and not 100% tested Table 2-13 SAP and BBP Timing (Continued) Num Characteristics Symbol Expression DSP_CLK @ 58.8 MHz Case Unit Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
