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DSP56600FM/AD Datasheet(PDF) 1 Page - NXP Semiconductors |
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DSP56600FM/AD Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 76 page  MOTOROLA SEMICONDUCTOR TECHNICAL DATA DSP56652 Order this document by: DSP56652/D Rev 1, 1/99 ©1998 MOTOROLA, INC. Preliminary This document contains information on a new product. Specifications and information herein are subject to change without notice. Advance Information INTEGRATED CELLULAR BASEBAND PROCESSOR Motorola designed the ROM-based DSP56652 to support the rigorous demands of the cellular subscriber market. The high level of on-chip integration in the DSP56652 minimizes application system design complexity and component count, resulting in very compact implementations. This integration also yields very low-power consumption and cost-effective system performance. The DSP56652 chip combines the power of MotorolaÕs 32-bit M¥CORE (TM) MicroRISC Engine (MCU) and the DSP56600 digital signal processor (DSP) core with on-chip memory, protocol timer, and custom peripherals to provide a single-chip cellular base-band processor. Figure 1 shows the basic block diagram of the DSP56652. Figure 1-1 DSP56652 System Block Diagram MCU - DSP INTERFACE X Data RAM MESSAGING UNIT Clocks DSP PLL MCU OnCE DSP OnCE ROM 4K x 32 Keypad I/F UART Smart Card I/F Queued SPI Serial Audio CODEC I/F Baseband CODEC I/F (7+1)K x 16 X Data ROM 10K x 16 Y Data ROM 10K x 16 Y Data RAM 6K x 16 Program RAM 512 x 24 Program ROM 48K x 24 1K x 16 RAM 56600 DSP MUX M¥CORE MicroRISC Core Core Protocol Timer Watch Dog Interrupt Timer Program Timer/ PWM Edge I/O External Memory RAM 512 x 32 AA1618 DSP56652 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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