S71GS256 datasheet(106/195 Pages) SPANSION

106 / 195 page

106

CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

Notes:

1. CLK may be HIGH or LOW, but must be static during synchronous read, synchronous write, burst suspend, and DPD

modes; and to achieve standby power during standby and active modes.

2. The WAIT polarity is configured through the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]

are affected. When only UB# is in the select mode, DQ[15:8] are affected.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any

external influence.

6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.

7. DPD is maintained until RCR is reconfigured.

Table 16. Bus Operations—Asynchronous Mode

MODE

POWER

CLK

(Note 1) ADV#

CE#

OE#

WE#

CRE

LB#/

UB#

WAIT

(Note 2)

DQ[15:0]

(Note 3)NOTES

Read

Active

Low-Z

Data-Out

Write

Active

Low-Z

Data-In

Standby

High-Z

5, 6

No Operation

Idle

Low-Z

4, 6

Configuration

Active

Low-Z

High-Z

DPD

Deep

Power-down

XXXX

High-Z

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