S71GS256 datasheet(108/195 Pages) SPANSION

108 / 195 page

108

CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

Bus Operating Modes

CellularRAM products incorporate a burst mode interface found on Flash products

targeting low-power, wireless applications. This bus interface supports asynchro-

nous, page mode, and burst mode read and write transfers. The specific interface

supported is defined by the value loaded into the BCR. Page mode is controlled

by the refresh configuration register (RCR[7]).

Asynchronous Mode

CellularRAM products power up in the asynchronous operating mode. This mode

uses the industry standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#).

READ operations (Figure 23) are initiated by bringing CE#, OE#, and LB#/UB#

LOW while keeping WE# HIGH. Valid data will be driven out of the I/Os after the

specified access time has elapsed. WRITE operations (Figure 24) occur when

CE#, WE#, and LB#/ UB# are driven LOW. During asynchronous WRITE opera-

tions, the OE# level is a “Don't Care,” and WE# will override OE#. The data to be

written is latched on the rising edge of CE#, WE#, or LB#/UB# (whichever occurs

first). Asynchronous operations (page mode disabled) can either use the ADV

input to latch the address, or ADV can be driven LOW during the entire READ/

WRITE operation.

During asynchronous operation, the CLK input must be held static (HIGH or LOW,

no transitions). WAIT will be driven while the device is enabled and its state

should be ignored.

Figure 22. Power-Up Initialization Timing

Note: ADV must remain LOW for page mode operation.

Figure 23. READ Operation (ADV# LOW)

VCC

VCCQ

tPU > 150 µs

Device Initialization

Device ready for

normal operation

VCC = 1.7 V

Data Valid

Address Valid

tRC = READ Cycle Time

CE#

OE#

WE#

ADDRESS

DATA

LB#/UB#

Don't Care

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