S71GS256 datasheet(112/195 Pages) SPANSION

112 / 195 page

112

CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

Mixed-Mode Operation

The device can support a combination of synchronous READ and asynchronous

WRITE operations when the BCR is configured for synchronous operation. The

asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH

or LOW) during the entire sequence. The ADV# signal can be used to latch the

target address, or it can remain LOW during the entire WRITE operation. CE# can

remain LOW when transitioning between mixed-mode operations with fixed la-

tency enabled. Note that the tCKA period is the same as a READ or WRITE cycle.

This time is required to ensure adequate refresh. Mixed-mode operation facili-

tates a seamless interface to legacy burst mode Flash memory controllers. See

Figure 55 for the “Asynchronous WRITE Followed by Burst READ” timing diagram.

WAIT Operation

The WAIT output on a CellularRAM device is typically connected to a shared, sys-

tem-level WAIT signal (see Figure 28 below). The shared WAIT signal is used by

the processor to coordinate transactions with multiple memories on the synchro-

nous bus.

Once a READ or WRITE operation has been initiated, WAIT goes active to indicate

that the CellularRAM device requires additional time before data can be trans-

ferred. For READ operations, WAIT will remain active until valid data is output

from the device. For WRITE operations, WAIT will indicate to the memory control-

ler when data will be accepted into the CellularRAM device. When WAIT

transitions to an inactive state, the data burst will progress on successive clock

edges.

CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT config-

uration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data

corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after

WAIT de-asserts, and for row boundary crossings, start one cycle after the WAIT

signal asserts.)

When using variable initial access latency (BCR[14] = 0), the WAIT output per-

forms an arbitration role for READ or WRITE operations launched while an on-chip

refresh is in progress. If a collision occurs, the WAIT pin is asserted for additional

clock cycles until the refresh has completed (see Figure 29 and Figure 30). When

the refresh operation has completed, the READ or WRITE operation will continue

normally.

WAIT is also asserted when a continuous READ or WRITE burst crosses the

boundary between 128-word rows. The WAIT assertion allows time for the new

row to be accessed, and permits any pending refresh operations to be performed.

WAIT will be asserted but should be ignored during asynchronous READ and

WRITE, and page READ operations.

Figure 28. Wired or WAIT Configuration

CellularRAM

External

Pull-Up/

Pull-Down

Resistor

Processor

READY

Other

Device

WAIT

Other

Device

WAIT

S71GS256 Datasheet(PDF) 112 Page - SPANSION

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