S71GS256 datasheet(111/195 Pages) SPANSION

111 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

111

Ad vance

Info rmat i o n

cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and

the burst restarted with a new CE# LOW/ADV# LOW cycle.

Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted

during delay.

Figure 26. Burst Mode READ (4-word burst)

Note: Non-default BCR settings: Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted

during delay.

Figure 27. Burst Mode WRITE (4-word burst)

Don't care

Undefined

Legend:

Latency Code 2 (3 clocks), variable

D[0]

D[1]

D[2]

D[3]

READ Burst Identified

(WE# = HIGH)

CLK

A[22:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

LB#/UB#

Address

Valid

Address

Valid

Latency Code 2 (3 clocks), variable

WRITE Burst Identified

(WE# = LOW)

CLK

A[22:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

LB#/UB#

D[0]

D[1]

D[2]

D[3]

Don't care

Legend:

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