S71GS256 datasheet(115/195 Pages) SPANSION

115 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

115

Ad vance

Info rmat i o n

Partial Array Refresh

Partial array refresh (PAR) restricts refresh operation to a portion of the total

memory array. This feature enables the device to reduce standby current by re-

freshing only that part of the memory array required by the host system. The

refresh options are full array, one-half array, one-quarter array, three-quarter ar-

ray, or none of the array. The mapping of these partitions can start at either the

beginning or the end of the address map (see Table 23). READ and WRITE oper-

ations to address ranges receiving refresh will not be affected. Data stored in

addresses not receiving refresh will become corrupted. When re-enabling addi-

tional portions of the array, the new portions are available immediately upon

writing to the RCR.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode

is used if the system does not require the storage provided by the CellularRAM

device. Any stored data will become corrupted when DPD is enabled. When re-

fresh activity has been re-enabled by rewriting the RCR, the CellularRAM device

will require 150µs to perform an initialization procedure before normal operations

can resume. During this 150µs period, the current consumption will be higher

than the specified standby levels, but considerably lower than the active current

specification.

DPD cannot be enabled or disabled by writing to the RCR using the software ac-

cess sequence; the RCR should be accessed using CRE instead.

Configuration Registers

Two user-accessible configuration registers define the device operation. The bus

configuration register (BCR) defines how the CellularRAM interacts with the sys-

tem memory bus and is nearly identical to its counterpart on burst mode Flash

devices. The refresh configuration register (RCR) is used to control how refresh

is performed on the DRAM array. These registers are automatically loaded with

default settings during power-up, and can be updated any time the devices are

operating in a standby state.

Access Using CRE

The configuration registers can be written to using either a synchronous or an

asynchronous operation when the configuration register enable (CRE) input is

HIGH (see Figure 31 and Figure 32). When CRE is LOW, a READ or WRITE oper-

ation will access the memory array. The register values are written via address

pins A[21:0]. In an asynchronous WRITE, the values are latched into the config-

uration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first;

LB# and UB# are “Don’t Care.” The BCR is accessed when A[19] is HIGH; the

RCR is accessed when A[19] is LOW. For reads, address inputs other than A[19]

are “Don’t Care,” and register bits 15:0 are output on DQ[15:0].

S71GS256 Datasheet(PDF) 115 Page - SPANSION

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