S71GS256 datasheet(110/195 Pages) SPANSION

110 / 195 page

110

CellularRAM Type 2

cellRAM_00_A0 October 4, 2004

Advan ce

In form ati o n

Burst Mode Operation

Burst mode operations enable high-speed synchronous READ and WRITE opera-

tions. Burst operations consist of a multi-clock sequence that must be performed

in an ordered fashion. After CE# goes LOW, the address to access is latched on

the rising edge of the next clock that ADV# is LOW. During this first clock rising

edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH,

Figure 26) or WRITE (WE# = LOW, Figure 27).

The size of a burst can be specified in the BCR either as a fixed length or contin-

uous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous

bursts have the ability to start at a specified address and burst through the entire

memory.

The latency count stored in the BCR defines the number of clock cycles that

elapse before the initial data value is transferred between the processor and Cel-

lularRAM device.

The WAIT output asserts as soon as a burst is initiated, and de-asserts to indicate

when data is to be transferred into (or out of) the memory. WAIT will again be

asserted if the burst crosses a row boundary. Once the CellularRAM device has

restored the previous row's data and accessed the next row, WAIT will be deas-

serted and the burst can continue (see Figure 47).

To access other devices on the same bus without the timing penalty of the initial

latency for a new burst, burst mode can be suspended. Bursts are suspended by

stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the

data bus while the burst is suspended, OE# should be taken HIGH to disable the

CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT out-

put will continue to be active, and as a result no other devices should directly

share the WAIT connection to the controller. To continue the burst sequence, OE#

is taken LOW, then CLK is restarted after valid data is available on the bus.

See “How Extended Timings Impact CellularRAM™ Operation” for restrictions on

the maximum CE# LOW time during burst operations. If a burst suspension will

Figure 25. Page Mode READ Operation (ADV# LOW)

CE#

OE#

WE#

ADDRESS

DATA

LB#/UB#

Don't Care

ADD[1]

ADD[2]

ADD[3]

tAA

D[0]

tAPA

D[1]

tAPA

D[2]

tAPA

D[3]

ADD[0]

S71GS256 Datasheet(PDF) 110 Page - SPANSION

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