TMS320DM6441 datasheet(7/229 Pages) TI

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Device Overview

2.1 Device Characteristics

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-1 provides an overview of the TMS320DM6441 SoC. The table shows significant features of the

device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the

C64x+ DSP, and the package type with pin count.

Table 2-1. Characteristics of the Processor

HARDWARE FEATURES

DM6441

DDR2 Memory Controller

DDR2 (16/32-bit bus width)

Asynchronous (8/16-bit bus width) RAM, Flash

Asynchronous EMIF (EMIFA)

(NOR, NAND)

Compact Flash

MMC/SD with secure data input/output (SDIO)

Flash Cards

SmartMedia/xD

Memory Stick/Memory Stick Pro

64 independent channels

EDMA

8 QDMA channels

2 64-bit general purpose (each configurable as 2

Timers

separate 32-bit timers)

64-bit watch dog

Peripherals

UART

3 (one with RTS and CTS flow control)

Not all peripherals pins

are available at the

SPI

1 (supports 2 slave devices)

same time (For more

I2C

1 (master/slave)

detail, see the Device

Configuration section).

Audio Serial Port [ASP]

10/100 Ethernet MAC with Management Data Input/Output

VLYNQ

HPI

1 (16-bit multiplexed address/data)

General-Purpose Input/Output Port

Up to 71

PWM

3 outputs

ATA/CF

1 (ATA/ATAPI-5)

1 input (VPFE)

Configurable Video Ports

1 output (VPBE)

USB 2.0

High speed client

Size (Bytes)

160KB RAM, 8KB ROM

DSP

•

32KB L1 program (L1P)/cache (up to 32KB)

•

80KB L1 data (L1D)/cache (up to 32KB)

•

64KB unified mapped RAM/cache (L2)

On-Chip Memory

Organization

ARM

•

16KB I-cache

•

8KB D-cache

•

16KB RAM

•

8KB ROM

CPU ID + CPU Rev ID

Control Status Register (CSR.[31:16])

0x1000

JTAGID register

JTAG BSDL_ID

0x0B70 002F

(address location: 0x01C4 0028)

DSP 405 MHz , ARM 202.5 MHz at 1.05 V

CPU Frequency

MHz

DSP 513 MHz, ARM 256 MHz at 1.2 V

DSP 2.47 ns, ARM 4.94 ns at 1.05 V

Cycle Time

DSP 1.9 ns, ARM 3.9 ns at 1.2V

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Device Overview

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