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TMS320DM6441 Datasheet(PDF) 81 Page - Texas Instruments |
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TMS320DM6441 Datasheet(HTML) 81 Page - Texas Instruments |
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81 / 229 page ![]() www.ti.com 4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating TMS320DM6441 Digital Media System-on-Chip SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007 Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Low/full speed: USB_DN and USB_DP 2.8 USB_DVDDAP3 V High speed: USB_DN and USB_DP 360 440 mV VOH High-level output voltage (3.3V I/O) DVDD33 = MIN, IOH = MAX 2.4 V High-level output voltage (1.8V I/O) DVDD18 = MIN, IOH = MAX DVDD - 0.45 V Low/full speed: USB_DN and USB_DP 0.0 0.3 V High speed: USB_DN and USB_DP -10 10 mV VOL Low-level output voltage (3.3V I/O) DVDD33 = MIN, IOL = MAX 0.4 V Low-level output voltage (1.8V I/O) DVDD18 = MIN, IOL = MAX 0.45 V VI = VSS to DVDD without opposing ±10 µA internal resistor VI = VSS to DVDD with opposing internal II Input current 50 100 250 µA pullup resistor (2) VI = VSS to DVDD with opposing internal -250 -100 -50 µA pulldown resistor (2) IOH High-level output current All peripherals 4 mA IOL Low-level output current All peripherals 4 mA VO = DVDD or VSS, internal pull disabled ±20 IOZ I/O Off-state output current µA VO = DVDD or VSS, internal pull enabled ±100 CVDD = 1.2 V, DSP clock = 513 MHz 659 Core (CVDD, APLLREFV, VDDA_1P1V, ICDD mA VDDA1P2LDO(3), CVDDDSP) supply current(4) CVDD = 1.05 V, DSP clock = 405 MHz 521 DVDD = 3.3 V, DSP clock = 513 MHz 6 3.3V I/O (DVDD33, USB_DVDDA3P3) supply IDDD mA current(4) DVDD = 3.3 V, DSP clock = 405 MHz 6 1.8V I/O (DVDD18, DVDDR2, DDR_VDDDLL, DVDD = 1.8 V, DSP clock = 513 MHz 98 IDDD PLLVDD18, VDDA_1P8V, USB_VDD1P8, mA DVDD = 1.8 V, DSP clock = 405 MHz 94 MXVDD, M24VDD) supply current(4) Ci Input capacitance 4 pF Co Output capacitance 4 pF (1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. (2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. (3) This pin is an internal LDO output and connected via 1 µF capacitor to USB_VSSA1P2LDO. (4) Measured under the following conditions: 60% DSP CPU utilization; ARM doing typical activity (peripheral configurations, other housekeeping activities); DDR2 Memory Controller at 50% utilization (135 MHz), 50% writes, 32 bits, 50% bit switching; 2 MHz ASP at 100% utilization; Timer0 at 100% utilization. At room temperature (25 °C) for typical process devices. The actual current draw varies across manufacturing processes and is highly application-dependent. Submit Documentation Feedback Device Operating Conditions 81 |
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