TMS320DM6441 datasheet(87/229 Pages) TI

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DSP Subsystem

ARM Subsystem

VICP

SYSCLK1

SYSCLK2

SYSCLK5

SCR

EDMA

VPFE

VPBE

DACs

DDR2 PHY

DDR2 VTP

DDR2 Mem Ctlr

PLLDIV1 (/1)

PLLDIV2 (/2)

BPDIV

PLL Controller 2

PLL Controller 1

PLLDIV3 (/3)

PLLDIV5 (/6)

PLLDIV2 (/2)

PLLDIV1 (/1)

SYSCLK3

Bypass Clock

UARTs (x3)

I2C

Timers (x3)

PWMs (x3)

ATA/CF

EMIF/NAND

EMAC

VLYNQ

MMC/SD

SPI

GPIO

ASP

HPI

USB 2.0

USB PHY

60 MHz

24 MHz

27 MHz

PCLK

VPBECLK

PLLDIV4 (/4)

Memory Stick

ARM INTC

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 5-4. DM6441 Clock Domains

(1)

Clock Modes (Frequency)

Subsystem

Fixed Ratio vs. PLL1

PLL Bypass

PLL Enabled

PLL1

–

27 MHz

405 MHz

DSP

1:1

27 MHz

405 MHz

ARM

1:2

13.5 MHz

202.5 MHz

EDMA3/VPSS

1:3

9 MHz

135 MHz

Peripherals

1:6

4.5 MHz

67.5 MHz

(1)

These table values assume a MXI/CLKIN of 27 MHz and a PLL1 multiplier equal to 15.

Figure 5-6. PLL1 and PLL2 Clock Domain Block Diagram

For further detail on PLL1 and PLL2, see the structure block diagrams Figure 5-7 and Figure 5-8,

respectively.

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