TMS320DM6441 datasheet(73/229 Pages) TI

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TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 3-23. VLYNQ Control, EMIFA, and GPIO Pin Multiplexing

PINMUX0 REGISTER BIT FIELDS

MULTIPLEXED PINS

EM_CS5/

EM_CS4/

VLYNQEN

VLSCREN

AECS5

AECS4

GPIO[8]/

GPIO[9]/

VLYNQ_CLOCK

VLYNQ_SCRUN

GPIO[8]

GPIO[9]

GPIO[8]

EM_CS4

EM_CS5

GPIO[9]

EM_CS5

EM_CS4

VLYNQ_CLOCK

GPIO[9]

VLYNQ_CLOCK

EM_CS4

VLYNQ_CLOCK

VLYNQ_SCRUN

Table 3-24. VLYNQ Data, EMIFA, and GPIO Pin Multiplexing

PINMUX0

MULTIPLEXED PINS

BIT FIELDS

EM_A[21]/

EM_A[20]/

EM_A[19]/

EM_A[18]/

EM_A[17]/

EM_A[16]/

EM_A[15]/

EM_A[14]/

VLYNQEN

VLYNQWD

GPIO[10]/

GPIO[11]/

GPIO[12]/

GPIO[13]/

GPIO[14]/

GPIO[15]/

GPIO[16]/

GPIO[17]/

VL_TXD0

VL_RXD0

VL_TXD1

VL_RXD1

VL_TXD2

VL_RXD2

VL_TXD3

VL_RXD3

EM_A[21]/

EM_A[20]/

EM_A[19]/

EM_A[18]/

EM_A[17]/

EM_A[16]/

EM_A[15]/

EM_A[14]/

GPIO[10](1)

GPIO[11](1)

GPIO[12](1)

GPIO[13](1)

GPIO[14](1)

GPIO[15](1)

GPIO[16](1)

GPIO[17](1)

VL_TXD0

VLRXD0

EM_A[19]/

EM_A[18]/

EM_A[17]/

EM_A[16]/

EM_A[15]/

EM_A[14]/

GPIO[12](1)

GPIO[13](1)

GPIO[14](1)

GPIO[15](1)

GPIO[16](1)

GPIO[17](1)

VL_TXD0

VLRXD0

VL_TXD1

VLRXD1

EM_A[17]/

EM_A[16]/

EM_A[15]/

EM_A[14]/

GPIO[14](1)

GPIO[15](1)

GPIO[16](1)

GPIO[17](1)

VL_TXD0

VLRXD0

VL_TXD1

VLRXD1

VL_TXD2

VLRXD2

EM_A[15]/

EM_A[14]/

GPIO[16](1)

GPIO[17](1)

VL_TXD0

VLRXD0

VL_TXD1

VLRXD1

VL_TXD2

VLRXD2

VL_TXD3

VLRXD3

(1)

This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9.

3.5.6.6 Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing

The multiplexing of the CLK_OUT1 and Timer0 Input (Timer 0 only) functions is shown in Table 3-25.

Table 3-25. Timer0 Input, CLK_OUT1, and GPIO Pin

Multiplexing

PINMUX1 REGISTER BIT FIELDS

MULTIPLEXED PINS

CLK_OUT1/

TIMIN

CLK1

TIM_IN/

GPIO[49]

CLK_OUT1

TIM_IN

3.5.6.7 ASP, SPI, I2C, ATA, and GPIO Pin Multiplexing

When the ASP, SPI, or I2C serial port functions are not selected, their pins may be used as GPIOs as

seen in Table 3-26, Table 3-27, and Table 3-28. The SPI_EN1 pin can also function as the HDDIR buffer

control when ATAEN is selected and the HDIREN bit is set.

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