TMS320DM6441 datasheet(27/229 Pages) TI

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TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2)

DESCRIPTION

NAME

NO.

EM_WAIT/

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.

(RDY/BSY)/

I/O/Z

DVDD18

For EMIFA, it is wait state extension input EM_WAIT.

IORDY

EM_OE/

(RE)/

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.

I/O/Z

DVDD18

(IORD)/

For EMIFA, it is output enable output EM_OE.

DIOR

EM_WE

(WE)

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For

I/O/Z

DVDD18

(IOWR)/

NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE.

DIOW

This pin is multiplexed between EMIFA, ATA/CF, and HPI.

For EMIFA, this is the Bank Address 0 output (EM_BA[0]).

EM_BA[0]/

When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of

DA0/

I/O/Z

DVDD18

the byte address.

HINT

When connected to a 16-bit asynchronous memory, this pin has the same function

as EMIF address pin 22 (EM_A[22]).

In HPI mode, it is the host interrupt output HINT.

This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.

For EMIFA, this is the Bank Address 1 output EM_BA[1].

EM_BA[1]/

When connected to a 16 bit asynchronous memory this pin is the lowest order bit of

DA1/

I/O/Z

DVDD18

the 16-bit word address.

GPIO52

When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the

address.

EM_A[21]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO10/

I/O/Z

DVDD18

For EMIFA, it is address bit 21 output EM_A[21].

VLYNQ_TXD0

EM_A[20]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO11/

I/O/Z

DVDD18

For EMIFA, it is address bit 20 output EM_A[20].

VLYNQ_RXD0

EM_A[19]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO12/

I/O/Z

DVDD18

For EMIFA, it is address bit 19 output EM_A[19].

VLYNQ_TXD1

EM_A[18]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO13/

I/O/Z

DVDD18

For EMIFA, it is address bit 18 output EM_A[18].

VLYNQ_RXD1

EM_A[17]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO14/

I/O/Z

DVDD18

For EMIFA, it is address bit 17 output EM_A[17].

VLYNQ_TXD2

EM_A[16]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO15/

I/O/Z

DVDD18

For EMIFA, it is address bit 16 output EM_A[16].

VLYNQ_RXD2

EM_A[15]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO16/

I/O/Z

DVDD18

For EMIFA, it is address bit 15 output EM_A[15].

VLYNQ_TXD3

EM_A[14]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO17/

I/O/Z

DVDD18

For EMIFA, it is address bit 14 output EM_A[14].

VLYNQ_RXD3

EM_A[13]/

This pin is multiplexed between EMIFA and GPIO.

I/O/Z

DVDD18

GPIO18

For EMIFA, it is address bit 13 output EM_A[13].

EM_A[12]/

This pin is multiplexed between EMIFA and GPIO.

I/O/Z

DVDD18

GPIO19

For EMIFA, it is address bit 12 output EM_A[12].

EM_A[11]/

This pin is multiplexed between EMIFA and GPIO.

I/O/Z

DVDD18

GPIO20

For EMIFA, it is address bit 11 output EM_A[11].

EM_A[10]/

This pin is multiplexed between EMIFA and GPIO.

I/O/Z

DVDD18

GPIO21

For EMIFA, it is address bit 10 output EM_A[10].

EM_A[9]/

This pin is multiplexed between EMIFA and GPIO.

I/O/Z

DVDD18

GPIO22

For EMIFA, it is address bit 9 output EM_A[9].

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