TMPR4925 datasheet(272/590 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-10

Table 10.3.3 Initiator Access Space Properties Register

Enable

Word Swap

Memory Space 0

BusMasterEnable & G2PCFG.G2PM0EN

G2PCFG.BSWAPM0

Memory Space 1

BusMasterEnable & G2PCFG.G2PM1EN

G2PCFG.BSWAPM1

Memory Space 2

BusMasterEnable & G2PCFG.G2PM2EN

G2PCFG.BSWAPM2

I/O Space

BusMasterEnable & G2PCFG.G2PIOEN

G2PCFG.BSWAPIO

BusMasterEnable:

Host mode:

PCI State Command Register Bus Master Bit (PCISTATUS.BM)

Satellite mode: Command Register Bus Master bit

10.3.5

Target Access (PCI Bus

→ G-Bus Address Conversion)

During PCI target access, the PCI Bus address of the Bus transaction issued by the PCI Bus is

converted into a G-Bus address and is used to issue a Bus transaction on the G-Bus. 32-bit PCI Bus

addresses are used on the PCI Bus. Also, 32-bit physical addresses are used on the G-Bus.

Three memory access windows and one I/O access window can be set in the PCI bus space (Figure

10.3.5). The size of each memory window is variable from 1 MByte to 512 MBytes. The size of the I/O

windo is variable from 256 Bytes to 64 Kbytes. When Bus transactions to these access windows is

issued on the PCI Bus, these Bus transactions are accepted as PCI target devices. The PCI Bus Address

is converted into G-Bus addresses, then Bus transactions are issued to the G-Bus.

The memory space window responds to the PCI memory space access command. The I/O space

window responds to the PCI I/O space access command.

Figure 10.3.5 Target Access Memory Window

Memory Access Window

I/O Access Window

0x00_0000_0000

0xFFFF_FFFF

0x0000_0000

0x00_0000_0000

0xFFFF_FFFF

PCI I/O Space

G-Bus Space

PCI Memory Space

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