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TMPR4925 Datasheet(PDF) 314 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 314 Page - Toshiba Semiconductor |
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314 / 590 page ![]() Chapter 10 PCI Controller 10-52 10.4.25 PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0xD10C This register is only valid when using the on-chip PCI Bus Arbiter. 31 16 Reserved : Type : Initial value 15 10 Reserved BMIE R/W : Type 0 : Initial value Bits Mnemonic Field Name Description 31:1 Reserved 0BMIE Broken Master Detected Interrupt Enable Broken Master Detected Interrupt Enable (Initial value: 0, R/W) Generates an interrupt when a Broken Master is detected. 1: Generates an interrupt. 0: Does not generate an interrupt. Figure 10.4.25 PCI Bus Arbiter Interrupt Mask Register |
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