Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

5. Pinning information

5.1. Pinning

74ALVT16823

1MR

1CP

1OE

1CE

1Q0

1D0

GND

GND

1Q1

1D1

1Q2

1D2

VCC

VCC

1Q3

1D3

1Q4

1D4

1Q5

1D5

GND

GND

1Q6

1D6

1Q7

1D7

1Q8

1D8

2Q0

2D0

2Q1

2D1

2Q2

2D2

GND

GND

2Q3

2D3

2Q4

2D4

2Q5

2D5

VCC

VCC

2Q6

2D6

2Q7

2D7

GND

GND

2Q8

2D8

2OE

2CE

2MR

2CP

001aad403

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

Fig. 4. Pin configuration SOT364-1 (TSSOP56)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8 54, 52, 51, 49, 48, 47, 45, 44, 43 data inputs

1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8 3, 5, 6, 8, 9, 10, 12, 13, 14

data outputs

2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8 42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs

2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8 15, 16, 17, 19, 20, 21, 23, 24, 26 data outputs

1MR, 2MR

1, 28

master reset input (active-LOW)

1OE, 2OE

2, 27

output enable inputs (active LOW)

1CP, 2CP

56, 29

clock pulse inputs (active rising edge)

1CE, 2CE

55, 30

clock enable input (active-LOW)

GND

4, 11, 18, 25, 32, 39, 46, 53

ground (0 V)

VCC

7, 22, 35, 50

supply voltage

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

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