Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

10.1. Waveforms and test circuit

001aaa256

nCP input

nQn output

tPHL

tPLH

tW

VOH

VI

GND

VOL

VM

VM

VM

1/fmax

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 5. Propagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width HIGH and maximum clock

frequency

001aad401

VM

input nDn,

nCE

input nCP

VM

VM

VM

VM

VM

tsu(H)

th(H)

tsu(L)

th(L)

GND

GND

VI

VI

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 6. Data set-up and hold times

input nMR

input nCP

output nQn

tPHL

tWL

trec

VM

GND

VOH

VOL

GND

VM

VM

VM

001aad400

VI

VI

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 7. Master reset pulse width, master reset to output delay and master reset to clock recovery time

74ALVT16823

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Product data sheet

Rev. 6 — 20 October 2020

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