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UPD75P3018A Datasheet(PDF) 6 Page - Renesas Technology Corp |
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UPD75P3018A Datasheet(HTML) 6 Page - Renesas Technology Corp |
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6 / 66 page ![]() µPD75P3018A 4 Data Sheet U11917EJ2V1DS 1. PIN CONFIGURATION (Top View) • 80-pin plastic QFP (14 × 14 mm) µPD75P3018AGC-3B9, 75P3018AGC-3B9-A, 75P3018AGC-8BT, 75P3018AGC-8BT-A • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD75P3018AGK-BE9, 75P3018AGK-9EU, 75P3018AGK-9EU-A Note Connect the VPP directly to VDD during normal operation. PIN IDENTIFICATIONS BIAS : LCD Power Supply Bias Control P70-P73 : Port7 BP0-BP7 : Bit Port 0-7 PCL : Programmable Clock BUZ : Buzzer Clock PTO0-PTO2 : Programmable Timer Output 0-2 COM0-COM3 : Common Output 0-3 RESET : Reset D0-D7 : Data Bus 0-7 S0-S31 : Segment Output 0-31 INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 SB0, SB1 : Serial Bus 0,1 INT2 : External Test Input 2 SCK : Serial Clock KR0-KR7 : Key Return 0-7 SI : Serial Input LCDCL : LCD Clock SO : Serial Output MD0-MD3 : Mode Selection 0-3 SYNC : LCD Synchronization P00-P03 : Port0 TI0-TI2 : Timer Input 0-2 P10-P13 : Port1 VDD : Positive Power Supply P20-P23 : Port2 VLC0-VLC2 : LCD Power Supply 0-2 P30-P33 : Port3 VPP : Programming Power Supply P40-P43 : Port4 Vss : Ground P50-P53 : Port5 X1, X2 : Main System Clock Oscillation 1, 2 P60-P63 : Port6 XT1, XT2 : Subsystem Clock Oscillation 1, 2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 S12 S13 S14 S15 2 3 4 S16 5 S17 6 S18 7 S19 8 S20 9 S21 10 S22 11 S23 12 S24/BP0 13 S25/BP1 14 S26/BP2 15 S27/BP3 16 S28/BP4 17 S29/BP5 18 S30/BP6 19 S31/BP7 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 P60/KR0 X2 X1 VPPNote XT2 59 58 57 56 XT1 55 VDD 54 P33/MD3 53 P32/MD2 52 P31/SYNC/MD1 51 P30/LCDCL/MD0 50 P23/BUZ 49 P22/PCL/PTO2 48 P21/PTO1 47 P20/PTO0 46 P13/TI0 45 P12/INT2/TI1/TI2 44 P11/INT1 43 P10/INT0 42 P03/SI/SB1 41 |
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