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UPD75P3018A Datasheet(PDF) 18 Page - Renesas Technology Corp |
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UPD75P3018A Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 66 page  µPD75P3018A 16 Data Sheet U11917EJ2V1DS 6. MEMORY CONFIGURATION 6.1 Program Counter (PC) ... 15 bits This is a 15-bit binary counter that stores program memory address data. Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, and the lower 14 bits are all valid. Figure 6-1. Configuration of Program Counter 6.2 Program Memory (PROM) ... 32768 × 8 bits The program memory consists of 32768 × 8-bit one-time PROM. The program memory address can be selected as shown below by setting the stack bank selection (SBS) register. Mk I Mode Mk II Mode Usable address 0000H to 3FFFH 0000H to 7FFFH Figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call instruction, during Mk I and Mk II modes. PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC Fixed at zero during Mk I mode |
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