UPD17062 datasheet(110/298 Pages) RENESAS

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108

µPD17062

11.2

INTERRUPT FUNCTION

The following peripheral hardware can use the interrupt function: the INTNC pin, timer, VSYNC pin, and serial

interface.

If the peripheral hardware satisfies the specified condition (e.g., a falling edge is input to the INTNC pin),

the interrupt function temporarily stops the program being executed and starts the exclusive processing

program.

The interrupt signal sent from the peripheral hardware at this time is called an interrupt request. Outputting

an interrupt signal can be expressed as “issuing an interrupt signal”. The exclusive processing program for

interrupts is called the interrupt processing routine.

When an interrupt is accepted, processing is branched to the program memory address (vector address)

specified for each interrupt source. Each interrupt processing routine can be started from this vector address.

Processing for the interrupt function can be divided into the processing done before interrupt acceptance

and the processing done after interrupt acceptance. First, the interrupt function operates until the interrupt

request from the peripheral hardware is accepted. Then, after the interrupt is accepted, the interrupt function

branches processing to the vector address and returns control to the program that was interrupted.

Sections 11.2.1 to 11.2.8 describe the functions of the blocks shown in Fig. 11-1.

11.2.1

Peripheral Hardware

There are four peripheral hardware interrupt functions: the INTNC pin, timer, VSYNC pin, and serial interface.

Interrupt request issuance conditions can be set for each type of peripheral hardware.

For example, the request issuance timing for the INTNC pin (rising or falling edge of the signal applied to

the INTNC pin) can be selected.

See Sections 11.3 to 11.7 for details of interrupt request issuance conditions for the peripheral hardware.

11.2.2

Interrupt Request Processing Block

An interrupt request processing block is provided for each type of peripheral hardware. This block controls

interrupt request permits an interrupt, and generates the vector address at interrupt acceptance.

Sections 11.2.3 to 11.2.8 describe the flags of the interrupt request processing block.

11.2.3

Interrupt Request Flags (IRQ

×××)

The interrupt request flags are set to 1 when an interrupt request is issued from the peripheral hardware.

These flags are reset to 0 when the interrupt request is accepted.

Because the interrupt request flags correspond one-to-one to the flags in the interrupt request register, they

can be read and written via the window register.

Writing a 1 via the window register has the same effect as issuing an interrupt request.

Once these flags are set, they are not reset until the corresponding interrupts are accepted or a 0 is written

via the window register.

Even if two or more interrupt requests are issued together, the interrupt request flags corresponding to

the unaccepted interrupts are not reset.

These flags are reset to 0 at power-on reset, clock stop, or CE reset.

UPD17062 Datasheet(PDF) 110 Page - Renesas Technology Corp

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