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UPD17062 Datasheet(PDF) 117 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 117 Page - Renesas Technology Corp |
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117 / 298 page  115 µPD17062 Fig. 11-3 Interrupt Acceptance Timing Chart (2) When two or more interrupts (e.g., rising edge at the INTNC pin and falling edge at the VSYNC pin) are used (a) Hardware priorities (b) Software priorities Instruction EI MOV WR, #0101B POKE INTPM, WR INTE INTNC pin IRQVSYN flag IPNC flag EI IPVSYN flag IRQNC flag VSYNC pin Interrupt cycle Interrupt cycle VSYNC pin interrupt acceptance INTNC pin interrupt holding period INTNC pin interrupt processing VSYNC pin interrupt processing VSYNC pin interrupt holding period INTNC pin interrupt acceptance Instruction EI MOV WR, #0100B POKE INTPM, WR INTE INTNC pin IRQNC flag IPNC flag EI IPVSYN flag IRQNC flag VSYNC pin MOV WR, #0101B POKE INTPM, WR INTNC pin interrupt holding period VSYNC pin interrupt acceptance INTNC pin interrupt processing INTNC pin interrupt acceptance VSYNC pin interrupt holding period VSYNC pin interrupt processing Interrupt cycle Interrupt cycle |
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