AD9549BCPZ datasheet(45/78 Pages) AD

45 / 78 page

Preliminary Technical Data

AD9549

Rev. PrA | Page 45 of 78

HARMONIC SPUR REDUCTION

The most significant spurious signals produced by the DDS are

harmonically related to the desired output frequency of the

DDS. The source of these harmonic spurs can usually be traced

to the DAC, and the spur level is in the -60dBc range. This ratio

represents a level that is about 10 bits below the full-scale

output of the DAC (10 bits down is 2-10, or 1/1024).

To reduce such a spur would require combining the original

signal with a replica of the spur but offset in phase by 180°.

This idea is the foundation of the technique used to reduce

harmonic spurs in the AD9549. Since the DAC has 14-bit

resolution, a -60dBc spur can be synthesized using only the

lower 4 bits of the DAC full scale range. That is, the 4 LSBs can

create an output level approximately 60dB below the full scale

level of the DAC (commensurate with a -60dBc spur). This fact

gives rise to a means of digitally reducing harmonic spurs or

their aliased images in the DAC output spectrum by digitally

adding a sinusoid at the input of the DAC with similar

magnitude as the offending spur but shifted in phase to produce

destructive interference.

Although the worst spurs tend to be harmonic in origin, the fact

that the DAC is part of a sampled system results in the

possibility of some harmonic spurs to appear in non-harmonic

locations in the output spectrum. For example, if the DAC is

sampled at 1 GHz and generates an output sinusoid of

170 MHz, the 5th harmonic would normally be at 850 MHz.

However, because of the sampling process, this spur appears at

150 MHz, only 20 MHz away from the fundamental. Hence,

when attempting to reduce DAC spurs it is important to know

the actual location of the harmonic spur in the DAC output

spectrum based on the DAC sample rate so that its harmonic

number can be reduced.

The mechanics of performing harmonic spur reduction is

shown in figure below. It essentially consists of two additional

DDS cores operating in parallel with the original DDS. This

enables the user to reduce two different harmonic spurs from

the 2nd to the 15th with 9 bits of phase offset control (±π) and 8

bits of amplitude control.

The dynamic range of the cancellation signal is further

augmented by a gain bit associated with each channel. When

this bit is set, the magnitude of the cancellation signal is

doubled by employing a 1-bit left-shift of the data. However,

the shift operation reduces the granularity of the cancellation

signal magnitude.

NOTE: Full-scale amplitude of a cancellation spur is

approximately -60dBc when the gain bit is a logic 0 and

approximately -54dBc when the gain bit is a logic 1.

S ysC lk

48-b it

Fre q ue n c y

Tun in g W ord

(F T W )

4 8 -b it A c c u m u la to r

An g le to

A m plitud e

C on v ers ion

DA C

(1 4 -b it)

DD S

P h ase

O ffset

I-S e t

DDS -

DDS +

2-C h an n el

H a rm onic

Fre que nc y

Ge n e ra to r

C H 1 C an c ellatio n P h ase O ffset

CH1 Ha rm o n ic Nu m b e r

H a rm o n ic S p u r C a n c e lla tio n

Sp u r

C a n c e lla tio n

En a b le

C H 1 C a nc e lla tio n M a gnitude

DDS

CH2 Ha rm o n ic Nu m b e r

C H 2 C an c ellatio n P h ase O ffset

C H 2 C a nc e lla tio n M a gnitude

CH 1

CH 2

H ead ro o m

C o rrectio n

CH 1 G a in

CH 2 G a in

Sh ift

Figure 32: Spur Reduction Technique

AD9549BCPZ Datasheet(PDF) 45 Page - Analog Devices

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