Z5380 datasheet(8/37 Pages) ZILOG

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Z5380 SCSI

PS97SCC0100

ZILOG

FUNCTIONAL DESCRIPTION (Continued)

Target Command Register.

Address 3 (Read/Write). When

connected as a target device, the Target Command Reg-

ister (Figure 9) allows the CPU to control the SCSI Bus

Information Transfer phase and/or to assert /REQ by writ-

ing this register. The Target Mode bit (Mode Register, bit

6) must be True (1) for bus assertion to occur. The SCSI

Bus phases are described in Table 2.

Figure 9. Target Command Register

Table 2. SCSI Information Transfer Phases

Bus Phase

Assert

I//O

C//D

/MSG

Data Out

Unspecified

Command

Message Out

Data In

Unspecified

Status

Message In

When connected as an Initiator with DMA Mode bit True, if

the phase lines (I//O, C//D, and /MSG) do not match the

phase bits in the Target Command Register, a phase

mismatch interrupt is generated when /REQ goes active.

To send data as an Initiator, the Assert I//O, Assert C//D,

and Assert /MSG bits must match the corresponding bits

in the Current SCSI Bus Status Register. The Assert /REQ

bit (bit 3) has no meaning when operating as an Initiator.

Bits 4, 5, 6, and 7 are not used.

Current SCSI Bus Status Register.

Address 4 (Read

Only). The Current SCSI Bus Register is a read-only

signals, plus the Data Bus parity bit. For example, an

Initiator device can use this register to determine the

current bus phase and to poll /REQ for pending data

transfers. This register may also be used to determine why

a particular interrupt occurred. Figure 10 describes the

Current SCSI Bus Status Register.

Figure 10. Current SCSI Bus Status Register

Select Enable Register.

Address 4 (Write Only). The

Select Enable Register (Figure 11) is a write-only register

which is used as a mask to monitor a signal ID during a

selection attempt. The simultaneous occurrence of the

correct ID bit, /BSY False, and /SEL True causes an

interrupt. This interrupt can be disabled by resetting all bits

in this register. If the Enable Parity Checking bit (Mode

selection.

Assert I//O

Assert C//D

Assert /MSG

Assert /REQ

"X"

Address: 3

(Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

/DBP

/SEL

I//O

C//D

/MSG

/REQ

/BSY

/RST

Address: 4

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

Address: 4

(Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Figure 11. Select Enable Register

PS009101-0201

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