Z5380 datasheet(9/37 Pages) ZILOG

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Z5380 SCSI

ZILOG

PS97SCC0100

Bus and Status Register.

Address 5 (Read Only). The

Bus and Status Register (Figure 12) is a read-only register

which can be used to monitor the remaining SCSI control

signals not found in the Current SCSI Bus Status Registers

(/ATN and /ACK), as well as six other status bits. The

following describes each bit of the Bus and Status Register

individually.

Figure 12. Bus and Status Register

Bit 0. /

ACK. Bit 0 reflects the condition of the SCSI Bus

control signal /ACK. This signal is normally monitored by

the Target device.

Bit 1.

/ATN. Bit 1 reflects the condition of the SCSI Bus

control signal /ATN. This signal is normally monitored by

the Target device.

Bit 2.

Busy Error. The Busy Error bit is active if an unex-

pected loss of the /BSY signal has occurred. This latch is

set whenever the Monitor Busy bit (Mode Register, bit 2) is

True and /BSY is False. An unexpected loss of /BSY

disables any SCSI outputs and resets the DMA Mode bit

(Mode Register, bit 1).

Bit 3.

Phase Match. The SCSI signals /MSG, C//D, and

I//O, represent the current information Transfer phase. The

Phase Match bit indicates whether the current SCSI Bus

phase matches the lower 3 bits of the Target Command

significant when operating as a Bus Initiator. A phase

match is required for data transfers to occur on the SCSI

Bus.

Bit 4.

Interrupt Request ACTIVE. Bit 4 is set if an enabled

interrupt condition occurs. It reflects the current state of the

IRQ output and can be cleared by reading the Reset Parity/

Interrupt Register.

Bit 5.

Parity Error. Bit 5 is set if a parity error occurs during

a data receive or a device selection. The Parity Error bit can

only be set (1) if the Enable Parity Check bit (Mode

reading the Reset Parity/Interrupt Register.

Bit 6.

DMA Request. The DMA Request bit allows the CPU

to sample the output pin DRQ. DRQ can be cleared by

asserting /DACK or by resetting the DMA Mode bit (bit 1)

in the Mode Register. The DRQ signal does not reset when

a phase-mismatch interrupt occurs.

Bit 7.

End of DMA Transfer. The End of DMA Transfer bit

is set if /EOP, /DACK, and either /IOR or /IOW are simulta-

neously active for at least 100 ns. Since the /EOP signal

can occur during the last byte sent to the Output Data

to ensure that the last byte has been transferred. This bit is

reset when the DMA Mode bit is reset (0) in the Mode

Input Data Register.

Address 6 (Read Only). The input

Data Register (Figure 13) is a read-only register that is

used to read latched data from the SCSI Bus. Data is

latched either during a DMA Target receive operation

when /ACK goes active or during a DMA Initiator receive

when /REQ goes active. The DMA Mode bit (bit 1) must be

set before data can be latched in the Input Data Register.

This register is read under DMA control using /IOR and

/DACK. Parity is optionally checked when the Input Data

/ACK

/ATN

Busy Error

Phase Match

Interrupt Request Active

Parity Error

DMA Request

End of DMA

Address: 5

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

Address: 6

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

Figure 13. Input Data Register

PS009101-0201

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