Z5380 datasheet(13/37 Pages) ZILOG

13 / 37 page

Z5380 SCSI

ZILOG

PS97SCC0100

Figure 21. Current SCSI Bus Status Register

Bus Phase Mismatch Interrupt

The SCSI phase lines are comprised of the signals I//O,

C//D, and /MSG. These signals are compared with the

corresponding bits in the Target Command Register: As-

sert I//O (bit 0), Assert C//D (bit 1), and Assert /MSG (bit 2).

The comparison occurs continually and is reflected in the

Phase Match bit (bit 3) of the Bus and Status Register. If the

DMA Mode bit (Mode Register, bit 1) is active and a phase

mismatch occurs when /REQ transitions from False to

True, an interrupt (IRQ) is generated.

A phase mismatch prevents the recognition of /REQ and

removes the chip from the bus during an Initiator send

operation (/DB7-/DB0 and /DBP will not be driven even

through the Assert Data Bus bit (Initiator Command Reg-

ister, bit 0) is active). This may be disabled by resetting the

DMA Mode bit (Note: It is possible for this interrupt to occur

when connected as a Target if another device is driving the

phase lines to a different state).

The proper values for the Bus and Status Register and the

Current SCSI Bus Status Register are displayed in Figures

22 and 23, respectively.

Figure 22. Bus and Status Register

Figure 23. Current SCSI Bus Status Register

Loss of BSY Interrupt

If the Monitor Busy bit (bit 2) in the Mode Register is active,

an interrupt is generated if the BSY signal goes False for at

least a bus-settle delay. This interrupt is disabled by

resetting the Monitor Busy bit. Register values are dis-

played in Figures 24 and 25.

/DBP

/SEL

I//O

C//D

/MSG

/REQ

/BSY

/RST

1XXX

/ACK

/ATN

Busy Error

Phase Match

Interrupt Request Active

Parity Error

DMA Request

End of DMA

000100

/DBP

/SEL

I//O

C//D

/MSG

/REQ

/BSY

/RST

1XXXX

PS009101-0201

Z5380 Datasheet(PDF) 13 Page - Zilog, Inc.

Z5380 Datasheet(HTML) 13 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL