PCD5096 datasheet(7/52 Pages) PHILIPS

7 / 52 page

1997 Jan 22

Philips Semiconductors

Preliminary speciﬁcation

Universal codec

PCD5096

6.3

Supply concept

The universal codec is designed for 3 V systems with a voltage range of 2.7 to 3.6 V. To allow connection to 5 V systems

the digital I/Os include level shifters. The core must run on 3.3 V and the peripheral supply on 5 V.

The five power supplies are listed in Table 2. Codec 1 and Codec 2 have their own power supplies: VDDA_1 and VDDA_2

respectively. VDD_PLL is the power supply dedicated to the PLL. The digital core and the memories are powered by VDD_2

and the digital peripherals by VDD_1. All digital pins (EARP_HF, EARM_HF, TEST, RESET, DI, DO, FSC, DCL, IO0, IO1,

CLK, SCL, SDA, A0 and A1) have internal level shifters, allowing the chip to be used in a 3 to 5 V environment.

Table 2

PCD5096 power supply

SUPPLY PAIR

ASSOCIATED DEVICE

VDD_1 and VSS_1

3 to 5 V peripheral supply

VDD_2 and VSS_2

3 V digital core supply

VDD_PLL and VSS_PLL

3 V PLL supply

VDDA_1 and VSSA_1

3 V Codec 1 supply

VDDA_2 and VSSA_2

3 V Codec 2 supply

Fig.3 PCx5096 supply rails with protection diodes.

handbook, full pagewidth

MBH862

VSS_1

VDD_1

VSSA_1

VDDA_1

VSSA_2

VDDA_2

VSS_2

VDD_2

VSS_PLL

VDD_PLL

PCD5096 Datasheet(PDF) 7 Page - NXP Semiconductors