PCD5096 datasheet(29/52 Pages) PHILIPS

29 / 52 page

1997 Jan 22

Philips Semiconductors

Preliminary speciﬁcation

Universal codec

PCD5096

11 CODEC TEST LOOPS

11.1

Test modes deﬁnition

For debug and evaluation purposes some test loops are

implemented in the speech codecs. These test loops are

activated by setting bits 13 to 8 in Control Register 0; see

Table 32. The signal flow in the test loops is shown in

Fig.16 and is described as follows:

• Normal operation: the codec is not in any of its test loop

modes; used for a normal application.

• 1 bit analog: this loop is intended for a separate

evaluation of the analog parts of the codec. A bitstream

interface (108fs) is available. Via TEST_INPUT

bitstream data is fed to the DAC and bitstream data from

the ADC is present on TEST_OUTPUT.

• 1 bit digital: this loop allows the evaluation of DDF and

DNS at the 108fs interface. Bitstream data from

TEST_INPUT is led to DDF and bitstream data from

DNS is available on TEST_OUTPUT.

• 1 bit closed loop: a connection between the bitstream

output of the ADC and the bitstream input of the DAC is

made. The bitstream data is also made available on

TEST_OUTPUT.

• 4fs codec: the 4fs codec loop gives access to the 4fs

interface for evaluation of DDF and DNS. 16-bit input

data is serially shifted in (two’s complement, MSB first)

on TEST_INPUT and the 14 MSBs are used by DNS.

On the other side 16 bits DDF output data is serially

shifted out on TEST_OUTPUT.

• 4f

s DSP: this loop allows evaluation of the DSP

software. On TEST_INPUT and TEST_OUTPUT, data

can be exchanged with the DSP (16 bits serially, 2’s

complement, MSB first).

• 4fs closed loop: a connection between the parallel

output of DDF and the input of DNS is made. The loop

data at 4fs can be monitored by shifting out bits serially

via TEST_OUTPUT.

• PCM probe: this special test loop allows the evaluation

of DSP software. The DSP software however, must

include a test mode in which any 16-bit data at a sample

rate of fs or 8 kHz (normally only present as numbers

within the DSP algorithm) is written to the output line that

is connected to DNS. While normally the data on this line

has a 4fs (32 kHz) sample rate, up to four (interleaved)

PCM signals can be monitored via TEST_OUTPUT.

Next to these hardware codec test loops there also may be

software DSP test loops, depending on the DSP software

version. For more information about the DSP software the

DSP manuals must be consulted.

In all codec test loop modes (except the normal operation

mode) the signals lines TEST_INPUT_x and

TEST_OUTPUT_x (x = 1 for Codec 1, x = 2 for Codec 2)

are mapped onto pins that normally have a different

function. Next to these data signals some timing signals

(FS4 and CLK3) are presented on pins. Table 33 shows

which pins are used in the codec test loop modes.

Table 32 Selection of functional test modes for Codec 1 and Codec 2

CDC1TM2

CDC1TM1

CDC1TM0

FUNCTIONAL TEST MODE

CDC2TM2

CDC2TM1

CDC2TM0

normal operation

1 bit analog

1 bit digital

1 bit closed loop

100

4fs codec

101

4fs DSP

110

4fs closed loop

PCM probe

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