AVR32AP datasheet(8/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

D - Debug state

The processor is in debug state when this bit is set. The bit is cleared at reset and should only be

modified by debug hardware, the breakpoint instruction or the retd instruction. Undefined behav-

iour may result if the user tries to modify this bit manually.

M2, M1, M0 - Execution Mode

These bits show the active execution mode. The different settings for the different modes are

shown in Table 2-1. M2 and M1 are cleared by reset while M0 is set so that the processor is in

supervisor mode after reset. These bits are modified by hardware, or execution of certain

instructions like scall, rets and rete. Undefined behaviour may result if the user tries to modify

these bits manually.

EM - Exception mask

When this bit is set, exceptions are masked. Exceptions are enabled otherwise. The bit is auto-

matically set when exception processing is initiated or Debug Mode is entered. Software may

clear this bit after performing the necessary measures if nested exceptions should be supported.

This bit is set at reset.

I3M - Interrupt level 3 mask

When this bit is set, level 3 interrupts are masked. If I3M and GM are cleared, INT3 interrupts

are enabled. The bit is automatically set when INT3 processing is initiated. Software may clear

this bit after performing the necessary measures if nested INT3s should be supported. This bit is

cleared at reset.

I2M - Interrupt level 2 mask

When this bit is set, level 2 interrupts are masked. If I2M and GM are cleared, INT2 interrupts

are enabled. The bit is automatically set when INT3 or INT2 processing is initiated. Software

may clear this bit after performing the necessary measures if nested INT2s should be supported.

This bit is cleared at reset.

I1M - Interrupt level 1 mask

When this bit is set, level 1 interrupts are masked. If I1M and GM are cleared, INT1 interrupts

are enabled. The bit is automatically set when INT3, INT2 or INT1 processing is initiated. Soft-

ware may clear this bit after performing the necessary measures if nested INT1s should be

supported. This bit is cleared at reset.

Table 2-1.

Mode bit settings

Mode

Non Maskable Interrupt

0Exception

Interrupt level 3

Interrupt level 2

Interrupt level 1

Interrupt level 0

Supervisor

Application

AVR32AP Datasheet(PDF) 8 Page - ATMEL Corporation

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