AVR32AP datasheet(55/181 Pages) ATMEL

55 / 181 page

32001A–AVR32–06/06

AVR32

4.2.2.7

TLB Accessed Register LO - TLBARLO

The TLBARLO register is a 32-bit register with 32 1-bit fields. Each of these fields contain the

Accessed bit for the corresponding UTLB entry. Bit 0 in TLBARLO correspond to UTLB entry 0,

bit 31 in TLBARLO correspond to UTLB entry 32.

Note: The contents of TLBARLO are reversed to let the Count Leading Zero (CLZ) instruction be

used directly on the contents of the registers. E.g. if CLZ returns the value four on the contents

of TLBARLO, then item four is the first unused item in the TLB.

4.2.3

Page Table Organization

The MMU leaves the page table organization up to the OS software. Since the page table han-

dling and TLB handling is done in software, the OS is free to implement different page table

organizations. It is recommended, however, that the page table entries (PTEs) are of the format

shown in Figure 4-4. This allows the loaded PTE to be written directly into TLBELO, without the

need for reformatting. How the PTEs are indexed and organized in memory is left to the OS.

Figure 4-4.

Recommended Page Table Entry format

4.2.4

TLB organization

The TLB is used as a cache for the page table, in order to speed up the virtual memory transla-

tion process. A single TLB is implemented in AVR32 AP, with 32 entries. The TLB is configured

as shown in Table 4-5.

Figure 4-5.

TLB organization

The A bit is the Accessed bit. This bit is set when the TLB entry is loaded with a new value using

the tlbw instruction. It is cleared whenever the TLB matching process finds a match in the spe-

cific TLB entry. The A bit is used to implement pseudo-LRU replacement algorithms.

When an address look-up is performed by the TLB, the address section is searched for an entry

matching the virtual address to be accessed. The matching process is described in chapter

4.2.5.

PFN

87 65 43 21

VPN[21:0]

ASID[7:0]

PFN[21:0]

AP[2:0]

Entry 0

VPN[21:0]

ASID[7:0]

PFN[21:0]

AP[2:0]

Entry 1

VPN[21:0]

ASID[7:0]

PFN[21:0]

AP[2:0]

Entry 2

VPN[21:0]

ASID[7:0]

PFN[21:0]

AP[2:0]

Entry 3

VPN[21:0]

ASID[7:0]

PFN[21:0]

AP[2:0]

Entry 31

Address section

Data section

SZ[1:0]

AVR32AP Datasheet(PDF) 55 Page - ATMEL Corporation

AVR32AP Datasheet(HTML) 55 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL