TMP112ASLASHBSLASHN datasheet(19/47 Pages) TI1

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7.3.2.7 High-Speed (Hs) Mode

For the two-wire bus to operate at frequencies above 400 kHz, the master device must issue a Hs-mode master

code (0000 1xxx) as the first byte after a START condition to switch the bus to high-speed operation. The

TMP112 family does not acknowledge this byte, but switches the input filters on the SDA and SCL pins and

the output filters on the SDA pin to operate in Hs-mode, thus allowing transfers at up to 2.85 MHz. After the

Hs-mode master code has been issued, the master transmits a two-wire slave address to initiate a data-transfer

operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving

the STOP condition, the TMP112 family switches the input and output filters back to fast-mode operation.

7.3.2.8 Timeout Function

The TMP112 family resets the serial interface if the SCL pin is held low for 30 ms (typical) between a start

and stop condition. The TMP112 family releases the SDA line if the SCL pin is pulled low and waits for a start

condition from the host controller. To avoid activating the timeout function, maintain a communication speed of at

least 1 kHz for SCL operating frequency.

7.3.2.9 Timing Diagrams

The TMP112 family is two-wire, SMBus and I2C interface-compatible. Figure 7-4 to Figure 7-6 describe the

various operations on the TMP112 family. Bus definitions are:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low, when the SCL line is high, defines

a START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a

STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The TMP112 family can also be used for single byte updates. To update

only the MS byte, terminate the communication by issuing a START or STOP communication on the bus.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device

that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA

line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data transfer can be signaled by the master generating a

Not-Acknowledge ('1') on the last byte that has been transmitted by the slave.

7.3.2.9.1 Two-Wire Timing Diagrams

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TMP112

SBOS473J – MARCH 2009 – REVISED FEBRUARY 2024

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TMP112A/B/N Datasheet(PDF) 19 Page - Texas Instruments