TMP112ASLASHBSLASHN datasheet(32/47 Pages) TI1

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8.3.2 Layout Example

Serial Bus Traces

Pull-Up Resistors

Supply Bypass

Capacitor

Via to Power or Ground Plane

Via to Internal Layer

Supply Voltage

SCL

GND

ALERT

ADD0

V+

SDA

Ground Plane for

Thermal Coupling

to Heat Source

Heat Source

Figure 8-7. Layout Example (SOT563-6 package)

There are special considerations that need to be taken for the TMP112 X2SON package. These considerations

are due to the center pad being electrically connected to either address or alert (depending on the orderables

shown in Address and Alert Variant Device Target Address) and because of the dimensions of the package and

the pads. With the address option, the center pad can be directly connected with a trace on the same layer to the

desired pin of the device as shown in Figure 8-5.

When using the ALERT pin of the device, this signal can be either routed out in between the pads or on a

different layer using a via within the center pad as shown in Figure 8-6. Both of these methods have constraints

that must be considered as explained below. Ultimately, choosing one of these methods depends on the

specifications of the board manufacturing process:

• Routing in between pads introduces trace clearance and trace width limitations. As the maximum space

between pads is 0.26 mm (10.2 mil), assuming a trace width of 0.1 mm (4 mil) limits the minimum clearance

to 0.08 mm (3.15 mil).

• Routing on a different layer using a via has specific benefits to the user application. For instance,

minimum trace clearance and trace width are higher but require a via on the center pad with specific

dimensions. The via diameter must be less than 0.305 mm (13.78 mil) to keep the via smaller than the center

pad and a minimum drill diameter of 0.1 mm (4 mil) can be assumed to avoid manufacturing issues. With this

TMP112

SBOS473J – MARCH 2009 – REVISED FEBRUARY 2024

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TMP112A/B/N Datasheet(PDF) 32 Page - Texas Instruments