TMP112ASLASHBSLASHN datasheet(24/47 Pages) TI1

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Table 7-7. Pointer Register Byte

7.5.2 Temperature Register

The Temperature Register of the TMP112 family is configured as a 12-bit read-only register (setting the EM bit

to 0 in the configuration register; see the Extended Mode section), or as a 13-bit read-only register (setting the

EM bit to 1 in the configuration register) that stores the output of the most recent conversion. Two bytes must be

read to obtain data and are listed in Table 7-8 and Table 7-9. Byte 1 is the most significant byte (MSB), followed

by byte 2, the least significant byte (LSB). The first 12 bits (13 bits in extended mode) are used to indicate

temperature. The least significant byte does not have to be read if that information is not needed.

Table 7-8. Byte 1 of Temperature Register

Note: Extended mode 13-bit configuration shown in parentheses.

BYTE

T11

T10

(T12)

(T11)

(T10)

(T9)

(T8)

(T7)

(T6)

(T5)

Table 7-9. Byte 2 of Temperature Register

Note: Extended mode 13-bit configuration shown in parentheses.

BYTE

(T4)

(T3)

(T2)

(T1)

(T0)

(0)

(1)

7.5.3 Configuration Register

The Configuration Register is a 16-bit read/write register used to store bits that control the operational modes of

the temperature sensor. Read/write operations are performed MSB first. Table 7-10 lists the format and power-up

and reset values of the configuration register. For compatibility, the first byte corresponds to the Configuration

Table 7-10. Configuration and Power-Up/Reset Formats

BYTE

POL

CR1

CR0

7.5.3.1 Shutdown Mode (SD)

The Shutdown mode bit saves maximum power by shutting down all device circuitry other than the serial

interface, reducing current consumption to typically less than 0.5 μA for SOT563-6 package and 0.15 μA for

X2SON-5 package. Shutdown mode is enabled when the SD bit = 1; the device shuts down when current

conversion is completed. When SD = 0, the device maintains a continuous conversion state.

7.5.3.2 Thermostat Mode (TM)

The Thermostat mode bit indicates to the device whether to operate in Comparator mode (TM = 0 shown in

Figure 7-9) or Interrupt mode (TM = 1 shown in Figure 7-10). For more information on Comparator and Interrupt

modes, see the High- and Low-Limit Registers section.

TMP112

SBOS473J – MARCH 2009 – REVISED FEBRUARY 2024

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