XRT83VSH28IB datasheet(63/74 Pages) EXAR

63 / 74 page

PRELIMINARY

XRT83VSH28

REV. P1.0.0

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

TABLE 32: MICROPROCESSOR REGISTER 0X0EH BIT DESCRIPTION

CHANNEL 0-7 (0X0EH-0X7EH)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

Reserved

This Register Bit is Not Used

D[6:0]

7SEG[6:0]

Segment Number Seven, Same Description as Register 0x08h

R/W

TABLE 33: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION

CHANNEL 0-7 (0X0FH-0X7FH)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

Reserved

This Register Bit is Not Used

D[6:0]

8SEG[6:0]

Segment Number Eight, Same Description as Register 0x08h

R/W

TABLE 34: MICROPROCESSOR REGISTER 0X80H, BIT DESCRIPTION

0X80H

NAME

FUNCTION

TYPE

RESET

VALUE

BIT #

SR/DR

Single-rail/Dual-rail Select: Writing a “1” to this bit configures

all 4channels in the XRT83VSH28 to operate in the Single-rail

mode.

Writing a “0” configures the XRT83VSH28 to operate in Dual-

rail mode.

R/W

ATAOS

Automatic Transmit All Ones Upon RLOS: Writing a “1” to

this bit enables the automatic transmission of All "Ones" data

to the line for the channel that detects an RLOS condition.

Writing a “0” disables this feature.

R/W

RCLKE

Receive Clock Edge: Writing a “1” to this bit selects receive

output data of all channels to be updated on the negative edge

of RCLK.

Wring a “0” selects data to be updated on the positive edge of

RCLK.

R/W

TCLKE

Transmit Clock Edge: Writing a “0” to this bit selects transmit

data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all

channels to be sampled on the falling edge of TCLK_n.

Writing a “1” selects the rising edge of the TCLK_n for sam-

pling.

R/W

XRT83VSH28IB Datasheet(PDF) 63 Page - Exar Corporation

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