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M68HC08 Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc |
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M68HC08 Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 288 page ![]() General Description MC68HC908BD48 — Rev. 2.1 Data Sheet Freescale Semiconductor General Description 33 NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC908BD48 do not require termination, termination is recommended to reduce the possibility of static damage. PTE2/VSYNCO This is a shared function pin. It can be configured as a standard I/O pin or the Hsync output from the sync processor. See Section 17. Input/Output (I/O) Ports and Section 16. Sync Processor. PTE1/HSYNCO This is a shared function pin. It can be configured as a standard I/O pin or the Vsync output from the sync processor. See Section 17. Input/Output (I/O) Ports and Section 16. Sync Processor. PTE0/SOG/TCH0 This is a shared function pin. It can be configured as a standard I/O pin, the SOG input to the sync processor, or the timer channel 0 I/O pin. See Section 17. Input/Output (I/O) Ports, Section 16. Sync Processor, and Section 10. Timer Interface Module (TIM). Table 1-1. Pin Functions PIN NAME PIN DESCRIPTION |
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