M68HC08 datasheet(94/288 Pages) FREESCALE

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System Integration Module (SIM)

Data Sheet

MC68HC908BD48 — Rev. 2.1

System Integration Module (SIM)

Freescale Semiconductor

Figure 7-5. Sources of Internal Reset

The active reset feature allows the part to issue a reset to peripherals

and other chips within a system built around the MCU.

7.4.2.1 Power-On Reset

When power is first applied to the MCU, the power-on reset module

(POR) generates a pulse to indicate that power-on has occurred. The

external reset pin (RST) is held low while the SIM counter counts out

4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU and

memories are released from reset to allow the reset vector sequence to

occur.

At power-on, the following events occur:

•

A POR pulse is generated.

•

The internal reset signal is asserted.

•

The SIM enables the oscillator to drive OSCXCLK.

•

Internal clocks to the CPU and modules are held inactive for 4096

OSCXCLK cycles to allow stabilization of the oscillator.

•

The RST pin is driven low during the oscillator stabilization time.

•

The POR bit of the SIM reset status register (SRSR) is set and all

other bits in the register are cleared.

ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST

COPRST

POR

INTERNAL

RESET

M68HC08 Datasheet(PDF) 94 Page - Freescale Semiconductor, Inc