M68HC08 datasheet(75/288 Pages) FREESCALE

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Central Processor Unit (CPU)

MC68HC908BD48 — Rev. 2.1

Data Sheet

Freescale Semiconductor

Central Processor Unit (CPU)

6.6.2 Stop Mode

The STOP instruction:

•

Clears the interrupt mask (I bit) in the condition code register,

enabling external interrupts. After exit from stop mode by external

interrupt, the I bit remains clear. After exit by reset, the I bit is set.

•

Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator

stabilization delay.

6.7 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break

interrupt by:

•

Loading the instruction register with the SWI instruction

•

Loading the program counter with $FFFC:$FFFD or with

$FEFC:$FEFD in monitor mode

The break interrupt begins after completion of the CPU instruction in

progress. If the break address register match occurs on the last cycle of

a CPU instruction, the break interrupt begins immediately.

A return-from-interrupt instruction (RTI) in the break routine ends the

break interrupt and returns the MCU to normal operation if the break

interrupt has been deasserted.

6.8 Instruction Set Summary

6.9 Opcode Map

See Table 6-2.

M68HC08 Datasheet(PDF) 75 Page - Freescale Semiconductor, Inc