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ST72324BJ2 Datasheet(PDF) 68 Page - STMicroelectronics |
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ST72324BJ2 Datasheet(HTML) 68 Page - STMicroelectronics |
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68 / 188 page  On-chip peripherals ST72324B 68/188 MCC beep control register (MCCBCR) MCCBCR Reset value: 0000 0000 (00h) 7 654 32 10 Reserved BC[1:0] -R/W Table 40. MCCBCR register description Bit Name Function 7:2 - Reserved, must be kept cleared 1:0 BC[1:0] Beep Control These 2 bits select the PF1 pin beep capability (see Table 41). The beep output signal is available in Active Halt mode but has to be disabled to reduce the consumption. Table 41. Beep frequency selection BC1 BC0 Beep mode with fOSC2 =8MHz 00 Off 0 1 ~2 kHz Output Beep signal ~50% duty cycle 1 0 ~1 kHz 11 ~500 Hz Table 42. Main clock controller register map and reset values Address (Hex.) Register label 7 6543 21 0 002Bh SICSR Reset value 0 AVDIE 0 AVDF 0 LVDRF x0 0 0 WDGRF x 002Ch MCCSR Reset value MCO 0 CP1 0 CP0 0 SMS 0 TB1 0 TB0 0 OIE 0 OIF 0 002Dh MCCBCR Reset value 0 0000 0 BC1 0 BC0 0 |
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