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ST72324BJ2 Datasheet(PDF) 71 Page - STMicroelectronics |
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ST72324BJ2 Datasheet(HTML) 71 Page - STMicroelectronics |
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71 / 188 page  ST72324B On-chip peripherals 71/188 Figure 36. Timer block diagram 1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 24: Interrupt mapping on page 46). MCU-peripheral interface Counter Alternate Output Compare register Output Compare Edge Detect Overflow Detect circuit 1/2 1/4 1/8 8-bit buffer ST7 internal bus Latch 1 OCMP1 ICAP1 EXTCLK fCPU Timer interrupt ICF2 ICF1 TIMD 0 0 OCF2 OCF1 TOF PWM OC1E EXEDG IEDG2 CC0 CC1 OC2E OPM FOLV2 ICIE OLVL1 IEDG1 OLVL2 FOLV1 OCIE TOIE ICAP2 Latch 2 OCMP2 8 8 8 low 16 8 high 16 16 16 16 (Control register 1) CR1 (Control register 2) CR2 (Control/Status register) CSR 6 16 8 8 8 8 8 8 EXEDG Timer internal bus circuit 1 Edge Detect circuit 2 circuit 1 Output Compare register 2 Input Capture register 1 Input Capture register 2 CC[1:0] pin pin pin pin pin register (See note 1) Counter register |
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