ST72324BJ2 datasheet(50/188 Pages) STMICROELECTRONICS

50 / 188 page

Power saving modes

ST72324B

50/188

Figure 27.

Active Halt mode flowchart

Peripheral clocked with an external clock source can still be active.

Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active Halt mode (such as

external interrupt). Refer to Table 24: Interrupt mapping on page 46 for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and restored when the CC register is

popped.

8.4.2

Halt mode

The Halt mode is the lowest power consumption mode of the MCU. It is entered by

executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status

and beeper (MCC/RTC) on page 64 for more details on the MCCSR register).

The MCU can exit Halt mode on reception of either a specific interrupt (see Table 24:

Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt,

the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to

stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the

interrupt or by fetching the reset vector which woke it up (see Figure 29).

When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable

interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,

including the operation of the on-chip peripherals. All peripherals are not clocked except the

ones which get their clock supply from another clock generator (such as an external or

auxiliary oscillator).

The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”

option bit of the option byte. The HALT instruction when executed while the Watchdog

system is enabled, can generate a Watchdog reset (see Section 14.1 on page 172) for more

details.

Halt instruction

Reset

Interrupt(2)

CPU

Oscillator

Peripherals(1)

I[1:0] bits

off

Fetch reset vector

or service interrupt

CPU

Oscillator

Peripherals

I[1:0] bits

off

XX(3)

CPU

Oscillator

Peripherals

I[1:0] bits

XX(3)

256 or 4096 CPU clock

cycle delay

(MCCSR.OIE = 1)

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