ST72324BJ2 datasheet(91/188 Pages) STMICROELECTRONICS

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ST72324B

On-chip peripherals

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10.4

Serial peripheral interface (SPI)

10.4.1

Introduction

The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication

with external devices. An SPI system may consist of a master and one or more slaves.

However, the SPI interface can not be a master in a multi-master system.

10.4.2

Main features

●

Full duplex synchronous transfers (on 3 lines)

●

Simplex synchronous transfers (on 2 lines)

●

Master or slave operation

●

6 master mode frequencies (fCPU/4 max.)

●

fCPU/2 max. slave mode frequency (see note)

●

SS Management by software or hardware

●

Programmable clock polarity and phase

●

End of transfer interrupt flag

●

Write collision, Master mode fault and Overrun flags

Note:

In slave mode, continuous transmission is not possible at maximum frequency due to the

software overhead for clearing status flags and to initiate the next transmission sequence.

Timer A: 36

Timer B: 46

OC1HR

Reset value

MSB

00000

LSB

Timer A: 37

Timer B: 47

OC1LR

Reset value

MSB

00000

LSB

Timer A: 3E

Timer B: 4E

OC2HR

Reset value

MSB

00000

LSB

Timer A: 3F

Timer B: 4F

OC2LR

Reset value

MSB

00000

LSB

Timer A: 38

Timer B: 48

CHR

Reset value

MSB

11111

LSB

Timer A: 39

Timer B: 49

CLR

Reset value

MSB

11110

LSB

Timer A: 3A

Timer B: 4A

ACHR

Reset value

MSB

11111

LSB

Timer A: 3B

Timer B: 4B

ACLR

Reset value

MSB

11110

LSB

Timer A: 3C

Timer B: 4C

IC2HR

Reset value

MSB

xxxxxxx

LSB

Timer A: 3D

Timer B: 4D

IC2LR

Reset value

MSB

xxxxxxx

LSB

Table 51.

16-bit timer register map and reset values (continued)

Address

(Hex.)

label

543210

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